The present invention relates to a data transfer device for transferring data between a system bus and a local memory.
FIG. 29 is a block diagram of a conventional data transfer device. The operation of the conventional data transfer device of FIG. 29 is briefly described as follows. Note that in the following description, it is assumed that the LSI denoted by the reference numeral 90 is a graphics processor. A local memory 20 includes a general region 21 and a frame buffer region 22. A host central processing unit (CPU) 1 transfers drawing commands to the general region 21 via an interface section 91. A drawing processor 94 reads drawing commands from the general region 21, executes drawing, and outputs the drawing results to the frame buffer region 22. A display processor 95 reads display data from the frame buffer region 22 and outputs the read display data to a monitor 81.
The host CPU 1 and the interface section 91 execute data processing using byte addresses. The drawing processor 94 and the display processor 95 execute pixel processing using X, Y coordinates. A SDRAM interface 96 has functions of generating addresses for the general region 21 and addresses for the frame buffer region 22. More specifically, the SDRAM interface 96 generates addresses basically in the order of byte addresses of the local memory 20 for the general region 21, and generates addresses in the order of raster scanning for the frame buffer region 22.
In the conventional data transfer device described above, therefore, the host CPU 1 transfers drawing commands to the general region 21 and leaves the entire drawing processing to the drawing processor 94. With recent improvement in the performance of the host CPU 1, however, it has become possible for the host CPU 1 to perform drawing processing in parallel with the drawing processing by the drawing processor 94, to improve the drawing performance and the drawing functions. In this parallel drawing, the host CPU 1 executes a program, performs drawing processing by defining an array corresponding to an X, Y coordinate system, and transfers pixel data obtained as a result of the processing to the frame buffer region 22.
During the data transfer to the frame buffer region 22, the host CPU 1 temporarily retains the generated pixel data in a first region of a main memory 2, and then transfers the data to a second region thereof, before transferring the data to the interface section 91. In the transfer of the data to the second region of the main memory 2, the host CPU 1 must generate an address for a position in the local memory 20 at which the pixel data is to be stored from the coordinates of the pixel data by executing a program or using a device driver and the like.
In the conventional data transfer device, therefore, the host CPU 1 must perform address conversion for data using the main memory 2 when it intends to transfer the data to the frame buffer region 22. This is a burden to the host CPU 1, and thus significantly deteriorates the system performance if the CPU performance has no room to spare. In addition, the number of cycles required for the address generation, which is performed between the host CPU 1 and the main memory 2 via a system bus, is several thousands of times as large as the number of cycles required for data transfer between the LSI 90 and the local memory 20 in some cases. This causes a problem of reducing the transfer rate.